Prix FOB
Obtenir le dernier prix|
100 Piece Minimum Order
Pays:
China
N ° de modèle:
K4H511638J-LCCC
Prix FOB:
Localité:
China
Prix de commande minimale:
-
Commande minimale:
100 Piece
Packaging Detail:
-
Heure de livraison:
-
Capacité de Fournir:
10000 Piece per Day
Payment Type:
T/T
Groupe de produits :
Personne àcontacter Mr. songhao
RM3022, Nan Guang Jie Jia Building, 3037 Shennan Road, Futian District, Shenzhen, Guangdong
1.0Â Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR**6, **3
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR**0
• Double-data-rate architecture; two data transfers per clock
cycle
• Bidirectional data strobe [DQS] (x4,x8) &Â
[L(U)DQS] (x*6)
• Four banks operation
• Differential clock s(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
 -. Read latency : DDR**6(2, 2.5 Clock), DDR**3(2.5 Clock),
DDR**0(3 Clock)Â Â Â Â
 -. Burst length (2, 4, 8)
 -. Burst type (sequential & interleave)
• All s except data & DM are sampled at the positive going
edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data
• LDM,UDM for write masking only (x*6)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/*4ms refresh)
• Maximum burst refresh cycle : 8
• *6pin TSOP II Pb-Free package
• RoHS compliant
| Pays: | China |
| N ° de modèle: | K4H511638J-LCCC |
| Prix FOB: | Obtenir le dernier prix |
| Localité: | China |
| Prix de commande minimale: | - |
| Commande minimale: | 100 Piece |
| Packaging Detail: | - |
| Heure de livraison: | - |
| Capacité de Fournir: | 10000 Piece per Day |
| Payment Type: | T/T |
| Groupe de produits : | IC components |
