Fieldbus Communicator IC Chip By Microcyber Corporation, China
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Fieldbus Communicator IC Chip

Fieldbus Communicator IC Chip

( Negotiable )

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Minimum Order

Localité:

-

Prix de commande minimale:

-

Commande minimale:

10 Piece

Packaging Detail:

box

Delivery Time:

15days

Supplying Ability:

-

Payment Type:

T/T

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Personne à contacter Mr. He

17-8 Wensu, Shenyang, Liaoning

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Description

General Description

 

FBC***9 is a fieldbus interface and controller IC which conforms to IEC ****8 filedbus physical layer definition. It supports typical embedded CPU and MCU, and satisfies the demands of high performance fieldbus masters or slavers.

FBC***9 contains Manchester data encoder and decoder on chip. It requires a medium interface and external filter for connection to a fieldbus system, and can automatically correct bus polarity. FBC***9 also contains 4k bytes embedded data RAM, applying DMA controller. The implementation of message transmission and address resolution can be executed without CPU intervention. The Rx and Tx data status is available in status registers of FBC***9, such as status of line operation, code error, frame loss, frame collision.

FBC***9 implement a portion of data-link layer function. Tx/Rx frame check sequence (FCS), *6 bits 1ms timer, *6 bits 1/*2ms timer, *6 bits octet time timer, frame code decoding and address resolution.

 

 

Features

 

FBC***9 is designed for fieldbus physical and part data link communication functions, details list below:

 

  • Supports line data rate *1.*5K Bit/S
  • Build-in Manchester Encoder/Decoder
  • Transmitter Jibber inhibit, receiver super long frame inhibit
  • Automatic parity recognize and correct
  • Message type and destination address detection automatically
  • Automatic transmitter and receiver frame check
  • Build-in three channels DMA controller,used to control data transmitting, receiving and address recognization looking up table memory management
  • 4k bytes asynchronous SRAM internal as communication buffer for transmitting, receiving and address lookup table memory
  • Length of Preamble, Start and Stop delimiter under software controlled
  • Build-in bus arbiter, CPU accessing internal SRAM correctly
  • Data link layer timer ( 1ms,1/*2 ms,octet time timer )
  • Designed lots of useful interrupt and status Registers
  • Compatibility with INTEL,ARM serials CPU
  • Internal loop back for test
  • STANDBY feature
  • Power supply: 2.7~5.5V
  • Power consumption: <**0uA
  • Operating temperature range: **0°C~*5°C
  • Available in **-pins TQFP package

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To:

Mr. He < Microcyber Corporation >

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