Description
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR**6, **3
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR**0
• Double-data-rate architecture; two data transfers per clock
cycle
• Bidirectional data strobe [DQS] (x4,x8) &
[L(U)DQS] (x*6)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR**6(2, 2.5 Clock), DDR**3(2.5 Clock),
DDR**0(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going
edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x*6)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/*4ms refresh)
• Maximum burst refresh cycle : 8
• *6pin TSOP II Pb-Free package
• RoHS compliant
